DIY DSE
Whenever I change anything in the D-Lev FPGA logic, I usually have to compile it many times in Quartus before hitting on a build that meets timing (or is close enough). The builds are tedious because I have to manually change the place & route seed between each build, and the build takes around 5 minutes on my aging PC, so there's a lot of sitting around and babysitting. This activity is known as "seed sweeping". The 180MHz processor clock domain is the hardest to reach timing closure, usually giving me results in the high 160s to mid 170s, and rarely a bit higher than 180.
Quartus has a built-in tool to automate this process called "Design Space Explorer". IMO DSE tries to do too much though, as it juggles various synthesis and place & route build parameters, when all you generally want is a seed sweep of a single initial synthesis result. I never felt all that secure about committing to the best timing result as there just were too many parameters in play. In their infinite wisdom, Intel / Altera decided to remove DSE from the free version of Quartus, which strikes me as kinda nuts as a business strategy, but who am I. They also removed the LogicLock feature, which might have helped me speed up the average build. And they 86ed the simulator a long time ago. By all means, let's hobble the hardware we're trying to sell by crippling critical software support of it, that's the ticket.
Anyway, I'm in the process of redesigning the D-Lev kit, and a new FPGA pinout seemed called for in order to help clean up the routing on the main printed circuit board. One of the really great features of FPGAs is the ability to move the pin assignments all over the place. I'm sure this has saved many a prototype from the trash.
Back to the build, I consulted with Chat GPT and it suggested a BASH script. The script opens the config text file that contains the seed number, deletes that line, and adds a new line with the new seed. It then performs a place & route followed by timing analysis by calling the Quartus command line executable versions of these Quartus modules. Finally, it greps the timing results file and reports the top speed of both clock domains to the screen and also by appending the results to a text file. It does all this in a loop, incrementing the seed until it reaches the maximum value specified in the script, and then stops.
Where has this script been all my life? I've spent many days just doing builds, particularly when designing and implementing the processor. What a relief!
Here's a the results of sweeping seeds 5 through 10:
Code:
Seed 5:
; 166.09 MHz ; 166.09 MHz ; pll_core|altpll_component|auto_generated|pll1|clk[0] ; ;
; 211.19 MHz ; 211.19 MHz ; pll_spdif|altpll_component|auto_generated|pll1|clk[0] ; ;
Seed 6:
; 166.92 MHz ; 166.92 MHz ; pll_core|altpll_component|auto_generated|pll1|clk[0] ; ;
; 212.49 MHz ; 212.49 MHz ; pll_spdif|altpll_component|auto_generated|pll1|clk[0] ; ;
Seed 7:
; 181.52 MHz ; 181.52 MHz ; pll_core|altpll_component|auto_generated|pll1|clk[0] ; ;
; 219.2 MHz ; 219.2 MHz ; pll_spdif|altpll_component|auto_generated|pll1|clk[0] ; ;
Seed 8:
; 172.8 MHz ; 172.8 MHz ; pll_core|altpll_component|auto_generated|pll1|clk[0] ; ;
; 212.09 MHz ; 212.09 MHz ; pll_spdif|altpll_component|auto_generated|pll1|clk[0] ; ;
Seed 9:
; 165.7 MHz ; 165.7 MHz ; pll_core|altpll_component|auto_generated|pll1|clk[0] ; ;
; 213.54 MHz ; 213.54 MHz ; pll_spdif|altpll_component|auto_generated|pll1|clk[0] ; ;
Seed 10:
; 175.38 MHz ; 175.38 MHz ; pll_core|altpll_component|auto_generated|pll1|clk[0] ; ;
; 209.16 MHz ; 209.16 MHz ; pll_spdif|altpll_component|auto_generated|pll1|clk[0] ; ;
Seed 7 meets 180MHz timing, so I picked that. The other clock has to hit 196.666666MHz, and it's rare that it doesn't.
