AFE Progress
I've been futzing around with the AFE circuitry again and feel like I've made some progress.
Above: The schematic. The stuff on the left is my rail-to-rail buffer, the middle is the coil and antenna, the right is attenuation, filtering, and squaring of the quadrature and in-phase signals that go back to the FPGA.
In particular, it would be highly desirable to roll off high frequencies from the antenna to the quadrature output, and this is supplied by R2/C2, R3/C3, and R4/C4. High pass filtering is supplied by C1/R1. The difficulty in doing this is obtaining a flat-ish phase response around the nominal operating range of the coil and antenna resonance. Previously I tried more or less identically filtering the in-phase leg to match the phase response of the quadrature leg, but this lead to excessive attenuation of the in-phase signal. I got the idea that all we really care about is matching the phase response around the operating zone, and after a bit of messing around with the simulation I found the simple C6/R6 high pass and C7/R7 low pass combo was entirely sufficient to do this, and with very little resulting attenuation.
Above: AC analysis from the coil drive to the quadrature filter output. Resonance is clearly around 440kHz, with significant roll-off on either side. Note the notch at ~1.4MHz.
Above: AC analysis from the antenna to the quadrature filter output. +/-3dB @ 55kHz / 4.2MHz; -10dB @ 10MHz; -47dB @ 100MHz; -16dB @ 10kHZ; -35dB @ 1kHz.
Above: AC analysis of the in-phase filter output (top red) and quadrature filter output (bottom green). You can see here that the phase responses of both overlap from 1kHz up to about 1MHz.
Above: AC analysis of the combined responses, again showing no phase deviation up to about 1MHz.
In simulation, the coil LC resonance Q is reduced by approximately 5% compared to the previous simple capacitive divider. Some Q reduction is to be expected due to the presence of the quadrature filter resistors, as they dissipate electrical energy as heat. 5% is negligible and a very good tradeoff.
Above: AFE circuit running on the bench. Breadboard is at the "cold" end of the 8mH coil, "hot" end is connected to a piece of aluminum flashing material. You can see the string of 10pF caps running down the center axis of the coil. So far, this super messy setup is running quite stable, even with scope probes attached.
How does it perform in real life? I've had it running on the bench now for several hours this morning, and it is very stable and very quiet in terms of phase noise - probably the best I've seen of any oscillator I've tested. It could just be that today is quiet in terms of environmental RF and ground noise, so I'll keep it going for a few days and report back. If all goes well, the main unresolved issue would then be how to adjust the amplitude of the quadrature filter output - I'm thinking of a few 10pF caps on the AFE PCB in series with the 10pF axial string that could be shorted out via jumpers.
[EDIT] A frequency dependent phase difference between the two legs can likely cause issues. The obvious one is reduction in antenna voltage. If the phase difference is non-linear then one would probably also worry about this impacting the linearity of the pitch field, though I'm not sure how to quantify that.
[EDIT2] If I touch the plate with a finger the DPLL locks to 1.5MHz, which is 3x the nominal. I believe this corresponds to the anti-resonance notch in the second image. The bad part is that it says locked there until I power cycle it. This is likely aggravated by the fact that the FPGA is running a load optimized for the smaller inductors. I need to extend the lower range and see if that helps. Some kind of false lock detector in the DPLL circuitry would be nice, but I'm unsure how to implement that without interfering with normal behavior. I think limiting the low end of operation is a mistake.
[EDIT3] Today, 24 hours later, the DPLL phase remains super quiet, so it seems filtering is a keeper. Playing around with touching the plate, it remains correctly locked with a slow press of my thumb. A quick press causes the 3rd harmonic lock. So it's not the range limitation that causes the false lock, it's the gestural bandwidth of the DPLL not tracking a really fast change in capacitance. I'm currently looking into ways to sense and recover from false lock situations.
