Teensy 4.0 600MHz ARM Cortex M-7 MCU - ideal for digital MCU based theremin?

Posted: 10/15/2019 2:34:53 PM
dewster

From: Northern NJ, USA

Joined: 2/17/2012

Vadim, you are indefatigable when it comes to this stuff!  Do you have a day job?

Is there any way to dither that source signal?  That's what I do in the FPGA, with a UI knob for each axis to control the amplitude (powers of 2).  Dither is now a triangle wave at 48kHz, so it gets perfectly nulled out by sampling the axes at 48kHz.  I invert the triangle for the other axis to have them dithering in opposite directions, though I'm not sure if that helps or not.

Posted: 10/15/2019 2:51:48 PM
Buggins

From: Theremin Motherland

Joined: 3/16/2017

I'm working full day. Software developer. Today I just feel sick, and stay home.
I'm trying not to spend time for this theremin stuff at work, but it does not always work

PWM signal is F_ref frequency, variable duty cycle. Depending on LP filter parameters, output of filter is similar to triangle wave or sine.

Posted: 10/16/2019 6:16:49 AM
Thierry

From: Colmar, France

Joined: 12/31/2007

In practice, oversampling is implemented in order to reduce cost and improve performance of an analog-to-digital converter (ADC) or digital-to-analog converter (DAC).[1] When oversampling by a factor of N, the dynamic range also increases a factor of N because there are N times as many possible values for the sum. However, the signal-to-noise ratio (SNR) increases by , because summing up uncorrelated noise increases its amplitude by , while summing up a coherent signal increases its average by N. As a result, the SNR increases by .

For instance, to implement a 24-bit converter, it is sufficient to use a 20-bit converter that can run at 256 times the target sampling rate. Combining 256 consecutive 20-bit samples can increase the SNR by a factor of 16, effectively adding 4 bits to the resolution and producing a single sample with 24-bit resolution.[3] While with N=256 there is an increase in dynamic range by 8 bits, and the level of coherent signal increases by a factor of N, the noise changes by a factor of =16, so the net SNR improves by a factor of 16, 4 bits or 24 dB.

Posted: 10/16/2019 6:32:43 AM
Thierry

From: Colmar, France

Joined: 12/31/2007

Another thought for that phase discriminator is if it can't be improved in the same way as it is and was done in analog FM receivers, going with the signal through a >60dB amplifier/limiter which was there to eliminate all amplitude changes and externally induced AM before the phase detection would happen and then being ways more precise. Look a bit into older Philips data sheets for analog FM receiver ICs from the 1980s...

A more modern approach could also be to not simply generate the reference frequency, but to do that twice, one at 0° and one at 90° and to multiply both with the phase shifted (and amplitude normalized/limited) antenna signal to get the I and Q vectors as it is done in direct conversion SDR receivers and to use these for detection purely in software.

Posted: 10/20/2019 6:43:40 PM
Buggins

From: Theremin Motherland

Joined: 3/16/2017

Thierry, thank you for explanations! Now it's clear why ADC oversampling/averaging is so limited.

For direct measure of signal periods, I believe, oversampling and averaging is working better. 
E.g. x4 oversampling gives 2 bits of measurement precision. And averaging of samples should work the same way.

Detecting phase shift of fixed reference frequency passed through High Q LC gives zoom in of 0.1pF C change into ~10% of output range.

It would be nice, instead of converting to analog with LP filter and back to digital form via ADC, measure phase shift or PWM duty cycle directly in digital form.
For FPGA, it's easy task. It may give much better precision than direct measure of oscillator frequency.

In MCU, some hardware support is needed. E.g. timer based PWM duty cycle measure with 150MHz timer ref clock, for 1ms interval will collect ~17 bits of data. I'm not sure if there is some way to get better precision here. 


Back to PWM->LP->ADC: let's try to find some way to increase sensitivity on long hand distance.
1) Bigger Q: antenna swing is ~250V, C_hand 0.1pF range closest to LC resonance has output range 0.36V of 3V ~ 10% of ACD range
2) When passing LC output to logic input, don't reduce amplitude by divider, use limiter (-0.7..5.7V using diodes in ESD protection cirqiut). This will give almost-square input, with sharp edges, with duty cycle very close to 50%
3) ADS1256 ADC chip at highest sample rate 30Ksps has 17.1 noise free bits, and 19.8 effective number of bits (ENOB). I believe we should use ENOB instead noise free bits in calculations. Difference between ENOB and noise free bits - ENOB uses noise RMS, while noise free bits used peak-to-peak noise.
4) ADS1256 averaging could add a few bits. E.g. ENOB for 2000 samples per second is 21.1 bits.
5) It's possible to use programmable gain amplifier (PGA) on ADC input: x2, x4, x8, x16, or x32 preamp. For measuring small signal changes near resonant frequency (near 2.5V for 5V VCC), it's possible to use differential input for ADC (2.5V as V_ref), and turn on PGA. E.g. x8 or x16 pre-amp makes sense for signals close to 2.5V. PGA doesn't add bits directly. E.g. x4 PGA doesn't add 2 bits of resolution, but only about 1 bit, like with averaging.
At 2Ksps with PGA=x16, ENOB is 19.3, and actually we have 4 bits zoom in input range, so total ENOB near middle of range is about 23.3 bits.


It should be enough up to hand-to-antenna ranges 80-90cm.
Latency of measure - 0.5-1ms

Need to check it experimentally.

Posted: 10/20/2019 8:13:39 PM
dewster

From: Northern NJ, USA

Joined: 2/17/2012

"Another thought for that phase discriminator is if it can't be improved in the same way as it is and was done in analog FM receivers, going with the signal through a >60dB amplifier/limiter which was there to eliminate all amplitude changes and externally induced AM before the phase detection would happen and then being ways more precise. Look a bit into older Philips data sheets for analog FM receiver ICs from the 1980s..."  - Thierry

This is what I do in the D-Lev, gain-up the sine wave into a square wave via CMOS inverters.

"2) When passing LC output to logic input, don't reduce amplitude by divider, use limiter (-0.7..5.7V using diodes in ESD protection cirqiut). This will give almost-square input, with sharp edges, with duty cycle very close to 50%"  - Vadim

I've wanted to do this forever.  Why knock the LC down (via C divider) to not clip, then amplify back up to clip?  Why not just somehow sample the large amplitude and let a clipper protect the logic input?  You would have better SNR that way.  The problem is a clipper like diodes is low impedance (though only in the clipping region), and will drastically skew your detected phase.  If you can find some way to do it you're a better man than me and I'm all ears.

[EDIT]

"For direct measure of signal periods, I believe, oversampling and averaging is working better.
E.g. x4 oversampling gives 2 bits of measurement precision. And averaging of samples should work the same way."

Precision ambiguity is usually modeled as noise.  Systematic ambiguity, such as truncation noise, is actually worse to deal with than noise.

Posted: 10/20/2019 8:43:04 PM
Thierry

From: Colmar, France

Joined: 12/31/2007

It’s difficult to clip a hi-Q resonant signal. Non-linear load risks to degrade the Q and clipping diodes add capacitance depending on the voltage.

I haven’t yet found a working solution. Still thinking about rather implementing a 4046 based volume detector, which risks to have other flaws and hurdles.

Posted: 10/26/2019 11:13:02 AM
Buggins

From: Theremin Motherland

Joined: 3/16/2017

Another solution for MCU based sensor - deeper to analog.
(Goal - avoid using external ADC and PLL clock gen)

Almost analog heterodyning for boths antennas, producing quadrature (pi/2 shifted sine) signal.
Signal on heterodyne output will not correspond directly to note pitch, but can be transformed to desired pitch / volume for sythesizer.


Oscillator outputs should be clean sine.
For each channel, generate reference frequency with two phases - shifted by pi/2, with frequency slightly higher than oscillator frequency with hand far from antenna.
Use switch IC like 4066 or something better to make heterodyne - pass sin() on 2 inputs, two phases on controls, two outputs filtered by 2-3 stages of RC filters are Focs-Fref with pi/2 shift between (quadrature). 2-channel ADC + atan2() gives samples of phase value. 
E.g. having 1KHz..10KHz ADC input for hand far/near antenna can be measured by ADC. Dual 10-12 bits of ADC should give about 10-12 bits of phase value.
Tracking / averaging of measured phase for sequential samples allows to get more bits (should be sqrt(k) additional bits for k averaging).

If audio I/O programmed as interrupt per sample (44100 or 48000Hz), for every sample it's possible to start ADC measurement for two values - two phases of either pitch or volume (volume can be measured at slower rate, allowing to measure other analog in inputs - e.g. 2 or 4 POTs).
In beginning of audio IRQ, there is a value of previous ADC available - 2 values may be converted to phase, and passed to corresponding averaging filter.
Current frequency of oscillator may be calculated with high precision, for pitch - converted to note, then note frequency, for volume - to volume control value.
44100Hz IRQ has enough CPU cycles for synthesis of next audio sample.


Another option: pass quadrature output of heterodyne to audio board Audio In - at least for pitch antenna...


P.S: I've received my order with two Teensy 4.0 and two Teensy 4.0 audio boards.

Posted: 11/1/2019 12:14:42 PM
Buggins

From: Theremin Motherland

Joined: 3/16/2017

Time Of Flight - Time To Digital

Nice method of theremin sensor implementation: use time-of-flight sensor IC (time-to-digital converter) to measure either phase shift or oscillator frequency.
Suitable component: TI TDC7200  

It's single channel meter of time difference between two signals. Resolution is 55ps (18GHz counter). It exceeds even possible FPGA designs.
Controlled via SPI interface (up to 20MHz clock). Has internal averaging capabilities - may provide measurement results once after averaging is done - to have lower IRQ rate (and better precision).

There is another device, TDC7201 with two channels, but it has only BGA package, which is impossible to solder with my skills.
So, two TDC7200 may be used for measurement of pitch and volume sensor outputs.

Approach one: oscillator as theremin sensor - TDC7200 could measure time between its edges to get frequency of oscillator.
Approach two: LC phase shift - pass reference frequency to LC, measure shift between input and output signals (or between raising/falling edges of PWM).

Using direct measure of oscillator frequency doesn't require reference frequency, so probably it's preferred.

There is TDC7201-ZAX-EVM evaluation board which can be used w/o necessity of BGA soldering, but it's big and expensive (>$75)

AMS TDC-GP22 is another possible dual channel device. It has 22ps resolution (or 90ps - unclear), and there are a lot of chip breakout boards / small modules with this chip.

UPD: two TDC-GP22 chips needed for two channels. Link to board on diymore. It's twice more expensive than single chip board: $25.
There is no averaging capabilities in GP22, so it makes sense to divide oscillator signal externally to get reasonable frequency value (+averaging).
It's hard to find documentation on this board.

AS6500 has good resolution (20ps), and doesn't have useless analog part (unlike GP22), looks fully suitable for theremin sensor, but price of dev board AS6500-QF_DK_RB is $112.5

Let's try to estimate sensitivity.
For 20ps == 50GHz, averaging frequency for 1ms, we have ~25..26 bits of period duration. Since oscillator frequency changes only by ~5% for distance range, 4 bits are removed. 21 bits left. 10cm of hand distance reduce C by ~4 times. But LC oscillator period value depends on C as sqrt(C)
Does it mean that T sensitivity decreases only by 1 bit (x1) with distance changed by 10cm?
If so, 90cm distance removes only 9 bits, and we still have 10-11 bits for next 10cm? Is there some mistake in my calculations?
I suspect, 10cm distance eats 3-4 bits of precision, not 1. Then, on 50-60cm number of bits will be decreased to near 0. Further averaging (e.g. latency 10ms instead of 1ms) could provide additional 10cm, but it still looks non impressive. I belive, 50GHz counter should be enough for theremin. What's wrong?


Posted: 11/2/2019 4:45:47 PM
Buggins

From: Theremin Motherland

Joined: 3/16/2017

TOF / TDC approach looks attractive but requires expensive ICs.

Probably, better theremin sensors implementation for Teensy 4.0 + Teensy SGTL5000 Audio Adaptor platform should use as much internal hardware as possible.

For pitch antenna, as much sensitivity as possible is required to have good enough resolutions at hand distances up to 80-90cm.
Internal timer resolution is only 150MHz, ADC has only 12bits. But there is another ADC available on platform, with dual channels, at least 16 bit resolution, sample rate 44100/48000 Hz, with ability to capture data via DMA w/o CPU load for every sample. It's Audio Adaptor Line In ADC. Probably, STGL is able to provide even more bits per sample.
Line In is capacitive decoupled, so only alternating voltage can be measured, in audible range, 50..20000Hz.

Proposed pitch sensor implementation: 

* LC oscillator on NPN provides clean sine wave with amplitude near 3V for far hand distance, dumped a bit (how much?) when hand approaches antenna.
* MCU generates two synchronous 50% duty cycle 90 degrees phase shift reference clocks, with frequency 500-1000Hz higher than max oscillator frequency.
* 2 Analog switches + LP filters + opamp buffer implement heterodyne (osc sine passed to both switch inputs, ref frequency signals are connected to switch control inputs, and outputs are passed to lowpass filters with 20KHz cutoff frequency). OpAmp probably could be useful as input and/or output buffer(s).
* Two channels of heterodyne output have clean sine wave with PI/2 phase shift. Frequency should be 100-1000Hz for hand far from antenna, and 8000-15000 for hand near antenna. Amplitude of signals passed to LineIn probably should be reduced to standard LineIn range (1V?)
* Amplitudes of output signals will be probably slightly different due to components precision. So, MCU should measure amplitudes of both channels during calibration to compensate. 0 level will be probably good enough.
* MCU will get sampled values from Audio Adaptor via I2S input using DMA by frames (default frame size in Teensy Audio Library looks too big but may be reduced). Another approach - to use per sample IRQ and read sampled values / write generated signal w/o DMA for every sample.
* Two phase shifted samples s1, s2 give us high precision heterodyne signal phase using atan2(s1, s2). Difference of phase between two samples provides signal frequency. Precision of single sample phase value depends on signal amplitude and 1/2 of max amp will be about 14 bits. Averaging would increase precision. 
* Measured frequency should be converted to note frequency according to calibration values and selected note range for usage in Synthesizer.

It's very close to classic analog theremins, but sensor output is quadrant, and frequency will not be used directly for playback, but instead will be converted to output range.

For volume antenna it's enough to have good resolution for distances up to 40-50 cm. 

Proposed Volume sensor implementation:

* MCU generates reference frequency close to LC resonance.
* Reference frequency passed to LC, phase shift between input and output is detected with XOR to produce PWM.
* PWM signal duty cycle is converted to voltage using LP filter.
* 12 bit ADC will be used to read sensor output voltage
* MCU may read result of previous measure and start new measure in audio frame or sample IRQ
* ADC value non-linearity is close to C_hand = A*atan(B*frequency_difference_from_resonant)
* C_hand then should be converted to linear hand distance, and then to volume multiplier

Since there are two ADC modules in Teensy 4.0, one may be reserved for Volume sensor, while second can be used for reading analog signals from pots / pedals.

Proposed sensors hardware looks simple and sensitive enough for me.
Reading of sensors doesn't require big CPU resources (e.g. unlike SPI connected sensor).
Low latency (no DMA, per-sample IRQ, latency = 1..2 samples) implementation is possible if 0.5..2ms frame looks too long.

Occupied pins for Pitch sensor:
   2 PWM output pins - reference frequency for heterodyne
   2 Line In channels from Audio Adaptor, no MCU pins used

Pins for Volume sensor:
   1 PWM pin for reference frequency generatin
   1 analog input pin for reading of PWM LP output

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