Spent some time looking at CIC filters and I think I understand them better now. Here is a good paper:
Equation 8 is the key, though it is clearer when explicitly expanded. CIC I/O response is:
1 + (z^-1) + (z^-2) + ... + (z^-(RM-1))
This is obviously a FIR filter with all coefficients =1, which is the definition of a boxcar or moving average filter with a rectangular window of width RM and a gain of RM. When decimating with a CIC we can place the comb downstream of the decimation, which is quite convenient because it reduces the required comb delay by a factor of 1/R. If M=1 and the comb is sampling every R samples, then what it is sampling is the last R input samples added together, which is the definition of an integrate and dump filter.
CIC makes sense in scenarios where the oversampling ratio is high and one needs to radically filter and decimate in order to get the sampling rate down to something more reasonable. A cascade of 3 seems to be the norm to get a good cutoff slope. Bit growth is an issue, particularly when cascading, though modulo math in the accumulators eases this. And the decimation ratio takes the place of lots of M storage, which is really convenient, but if you don't want to decimate then you have to pony up the storage.
Anyway, I'm back to first order integrate and dump with power of 2 periods. Though since interrupts shouldn't come in at more than a 1.5MHz rate I'm toying with the idea of putting an interrupt time stamp in the Hive register set, which could enable period timing with the interrupt mechanism alone, though it would pretty much tie up one thread. (But first I'm off in an attempt to rearrange the Hive guts for full 32 bit memory access.)
I'm still kind of concerned about aliasing. I don't believe I've really thought it out, particularly in the context of heterodyning. To reduce the probability of it, one could take the LC oscillator output and LPF the phase with a PLL or DPLL before heterodyning. Sampling and filter internal node truncation are huge cans of worms, analog filtering is a breeze compared to digital filtering. Even something as trivial as the CIC, which boils down to almost nothing, just about breaks my brain. (Though the CIC itself is a very clever arrangement.)
"analog filtering is a breeze compared to digital filtering. Even something as trivial as the CIC, which boils down to almost nothing, just about breaks my brain." - Dewster
LOL ;-) - Thats the one thing in the above post which I can fully understand and fully agree with!
More monkeying around with Hive:
The main change is full 32 bit memory reads / writes / literals. I haven't updated the simulator yet.
If time were more pressing (i.e. if I was smart) I would have used the tiniest FPGA available, done the minimum in there, and lashed it to a beaglebone black, hummingboard, or similar credit card sized ARM processor. You could have a real screen, implement any kind synthesis, and dial up more delay / reverb then you could shake a stick at. But it wouldn't feel as "embedded" to me, and there would likely be boring ass boot times to contend with.
Still debating whether to use LEDs or LCD for the data display. Got a 2 line LCD with tri-color LED backlight from Adafruit but haven't hooked it up to anything. LCDs are dogs to communicate with, but they are cheap and can show a reasonable amount of data. It's too bad they don't seem to make calculator LED displays anymore, I'd probably go with that, though the multiplexed drive might drive the capacitance sensing crazy, and there is always the awkward alpha representation problem. Am thinking of turning off any display electronics during play (except for the tuner which will likely NOT be multiplexed, but it will be PWM) for that reason.
You can still buy individual and dual 7 segment and 14 segment (alphanumeric) LED's @ about $1 / per display (Dual displays are fractionally cheaper than singles, per seg) and you can get LED dot matrix.. They do work out a lot more expensive than LCD though.
The only theremin related product I used an LCD display on was "Epsilon" - it was in the early days when I knew even less about theremins than I do now ;-) and had low antenna voltage... It was a nightmare! - The LCD was the major source of trouble, orders of magnitude more noisy than anything else.
As you will know I abandoned that project and started my long descent into theremin hell - I think Epsilon set me on the path to pedantic research and design leading me nowhere slowly... But experiments before I gave up Epsilon indicated a big (proportional) improvement the higher the antenna voltage, and other improvements from shielding the LCD cables - I desperately tried synchronising the LCD to the reference or some division thereof, but it was a complete module (I destroyed one trying to hack its smd circuitry).
"Am thinking of turning off any display electronics during play (except for the tuner which will likely NOT be multiplexed, but it will be PWM) for that reason."
I think my problems were mostly down to ignorance and stupidity - a kind of reckless confidence that seems to inflict many newcomers to theremin technology - it all looks so easy... ;-) With the series LC configuration you are employing, and if you build in the option of having the data display inactive when playing, I think you may well get away with PWM'in the pitch display..... And if it causes problems, IMO, omitting this display would be no great loss... ;-) - Sorry, its the only feature of your instrument who's value I doubt.
(I do wish I had thought about turning the display off when switching to "play" mode... Would have been a bit tricky - the display gave instructions to perform auto-calibration and low noise was required when doing this... but it could have turned off after issuing the instruction, then back on after acquiring the data, and then off when the user selected "play")
"You can still buy individual and dual 7 segment and 14 segment (alphanumeric) LED's @ about $1 / per display (Dual displays are fractionally cheaper than singles, per seg) and you can get LED dot matrix.. They do work out a lot more expensive than LCD though." - FredM
Thanks! Yes, I see them at Mouser and other places. Brightness is quite high for some of them. Might be able to get by with 2 lines of 8 chars, or a single line of 16. 8 chars is 32 bits hex, the largest I expect any value to be. Could have one line of 14 segment and one line of 7 segment if, for example, the top line is the identifier of the value and the bottom the hex value.
I suppose the LCD could be completely powered down to disable it if necessary. Gave mine 3.3V today and snooped around very briefly with a scope lead, but didn't see anything in the way of emissions. Perhaps I need to initialize it to see emissions? Other than what it's doing on its own, the LCD can be a fairly static thing, with no active data or clock going to it when no change is required. I don't think it will be terribly visible through a slab of red frosted plexiglas though (thinking of going red clear).
I wish the FPGA demo board had a better physical design for the on-board voltage regulators, I could power gobs of LEDs directly from all the spare pins. As it is the regulators get kind of hot. I could clip the leads and mount new ones off-board but that would be kind of fiddly.
One thing that occurred to me was the use of day-glo orange or other similarly tinted plexiglas, with UV LEDs underneath for the tuner - that might look pretty snappy!
"One thing that occurred to me was the use of day-glo orange or other similarly tinted plexiglas, with UV LEDs underneath for the tuner - that might look pretty snappy!" - Dewster
Depends on whether you want the LEDs to blur into each other or not - You certainly dont get sharp florescence, also, you lose a lot of the energy through the process - it is worth trying though.
I did an evaluation on an idea (pending patent) once where the inventor wanted two 'de-tuned' LEDs to illuminate a special translucent graduated (phosphorescent) filter - The idea was a simple analogue "bargraph" type display using just 2 leds who's brightnesses were inversely adjusted. ... Sadly it didn't work (the theory was so fatally flawed it should have been rejected at the first "crazy ideas" phase) - but it was one of those fun jobs which I actually got money for ;-)
Trivial first order integer low pass digital IIR filter with fixed cutoff:
Multiplication is single right shift (divide by 2) and it employs a single adder. I/O gain is 1. The form was found by taking the LPF form and setting the attenuation to 1/2, which allowed the replacement of the add and subtract with a single add.
Fcutoff should be Fsample/(4*pi). In reality, Fcutoff is quite a bit higher than this at ~Fsample/8.716 which was determined via graphical means (I was unable to find a simple mathematical expression / justification).
Maximum attenuation at Fsample/2 is around -9.5 dB.
Since it uses only a single add, a single register, and no multiplication, this filter can be quite inexpensively placed anywhere some rough and ready LPF action is desired (provided the fixed cutoff point is acceptable) and should run at high speed. Cascade 2 for more filtering!