Let's Design and Build a (mostly) Digital Theremin!

Posted: 9/25/2016 11:20:48 PM
oldtemecula

From: 60 Miles North of San Diego, CA

Joined: 10/1/2014

dewster said: When it comes to feedback sign, I find my first mental take is almost always wrong, so I was banging my head trying to get it to see a light that wasn't there!

Posted: 9/25/2016 11:31:16 PM
dewster

From: Northern NJ, USA

Joined: 2/17/2012

I hate to say it, but it kept me up until 2 AM.

Posted: 9/26/2016 8:45:25 PM
dewster

From: Northern NJ, USA

Joined: 2/17/2012

Interesting LC Buffer Behavior

Discovered this morning that I'm not giving the phase detector enough dynamic range (counter bits), which causes it to modulo roll over / under, which causes lock problems with lower frequencies - frequencies much lower than tank resonance.  Fixing this is simple and should make the phase lock much more robust and self-starting.  While looking into this I've been thinking of adding some sort of assist to the phase detector to generally improve the bandwidth it can cope with.  You have to do this kind of stuff very carefully, as it can easily introduce non-linearities and unintended behavior.  Since the LC is a low pass filter, the I/O phase delay will be near zero degrees below resonance, near 180 degrees above resonance, and 90 degrees at lock.  With this limited range one might think an XOR is ideally suited to the situation, and it pretty much is.  But the tank drive is a square wave, so the strong odd harmonics of a lower frequency driving the tank could confuse things, causing a lock to a harmonic rather than to the fundamental.

I've been aware that the buffer I'm using, an NPN / PNP pair arranged in a non-inverting follower configuration, has a rather large dead-band.  The drop across the emitters lowers the output voltage swing, though this probably isn't an issue.  The buffer can pull in both directions, but it doesn't provide a low impedance if the thing it is driving decides to pull the other way.  I haven't considered this to be an issue, since at resonance the tank doesn't do this, but when not at resonance it can and will, and I noticed some unexpected and rather nice behavior regarding this that I'd like to share because it means we can use a simple XOR phase detector over a very wide range of frequencies.

The above is a scope shot of the NPN/PNP buffer output driving the tank at the top, and the tank output (capacitive divider and twice inverted) on the bottom which feeds the FPGA board.  You can see the top signal amplitude is roughly two diode drops below the 3.3V supply, and that the tops and bottoms are somewhat concave, indicating current draw from the tank.  Note that the bottom signal lags by roughly 90 degrees, the lock condition for the phase detector, though to obtain the data shown here I am simply manually manipulating the drive frequency via the command line and the resonance frequency with my hand.

Above I've brought my hand near the antenna, dropping resonance / causing the drive frequency to be too high, which makes the phase difference larger than 90 degrees.  Note the buffer has spikes that go one diode drop beyond the supply as the collectors reverse bias and clamp to the supply rails.  The spikes are due to the buffer trying to drive the tank too early in the other direction, when it is still trying to pull current from the buffer.  Note that this isn't a huge deal in terms of the integrity of the lower signal being sent to the FPGA.

 

The above is what happens when the drive frequency is 1/3 of the resonance frequency.  "Bumps" at the resonance frequency can be seen riding on top of the drive, and they are fairly high amplitude due to the inability of the buffer to constrain the opposite swing.  This is reflected as dips in the signal going to the FPGA at bottom (so we wouldn't want to use an edge detecting phase detector here) but the overall duty cycle and phase are clearly correct (slightly larger than zero because the drive frequency is way below resonance) so the XOR result will be directionally correct and drive things to lock.  If the buffer presented a continuous low impedance to the tank we would see a sine wave on the bottom, and the XOR wouldn't know what to do with that, so the discontinuous output impedance is actually a plus.

The above is the 5th harmonic driving the tank, it isn't nearly as bad looking as the 3rd harmonic, and the signal going back to the FPGA will give the XOR a very clear indication of which way to drive the output frequency. 

And here is a view of the 7th harmonic driving the tank to resonance, it shouldn't be a problem either.  And this brings us near the bottom in terms of output frequency range of the numerically controlled periodic delay, so no other harmonics should be an issue, and the XOR should be able to lock over the entire range.

The only place phase gets ambiguous is when driving the tank above 4MHz or so, so if we start things out low it should seek out and lock to the fundamental without issue, and almost no matter what value inductor we use.  I haven't actually tried this out yet but I trust it will work.  If lock robustness is confirmed, I may make the pitch side oscillator purely digital hardware and only use software to process the operating point data.  The volume side will likely use a HW / SW combo loop, as previously discussed (ad nauseum - sorry about that, Chief).

Posted: 9/26/2016 10:02:37 PM
oldtemecula

From: 60 Miles North of San Diego, CA

Joined: 10/1/2014

Sorry about that Chief

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