[dewster] I had the idea that quadrature phase delay could be introduced by the 6800pF caps rather than a single capacitor at the output. The motivation here was to keep the current mirror gain as high as possible, and indeed you can see from the above that it provides a pretty good square wave going into the Vsense inverter input, and the phase is good. The delay of course varies with inductor value, unlike the integrating approach.
I believe this 90 degrees shift is similar to RC filter.
Not only changing of inductor, but as well hand movement would change the phase delay introduced by it.
Probably it makes sense to try improving integrator approach which always provide 90 degrees shift?
[dewster] The thing is, tapping off of the antenna with a capacitive divider is really pure, and the LC gain (i.e. Q) at that point is enormous, so by intuition alone it's rather easy to see why it is likely the most optimal solution so far, and for this approach - i.e. squaring up the sine wave and using that edge timing digitally. The most optimal in an absolute sense would likely be high speed AD conversion and some sort of best fit procedure in the FPGA.
Don't you consider using of comparator convert low amplitude sine to square?