**[WARNING: Please see EDIT2 below!]**

*"1) What current inductance values for your D-Lev pitch and volume are you using, and with your antenna elements what are your resonant frequencies (rough numbers are fine)?" - pitts8rh*

(with large plate antennae)

- pitch: 1mH, **1.25MHz**

- volume: 2mH, **917kHz**

*"2) What approximate loaded Qs are you getting for each side?"*

- pitch: 2.28Vpp @ 1pF | 195pF = 2.28Vpp * 196 =** 447Vpp**

- volume: 1.92Vpp @ 1pF | 195pF = 1.92Vpp * 196 =** 376Vpp**

- pitch Q = 447Vpp / 1.9Vpp =** 235**

- volume Q = 376Vpp / 1.9Vpp = **198**

Methods:

Vpp is measured at the AFE3 C divider, which in both cases consists of 1pF and 180pF. The Rigol 10x scope probe is ~15pF. This forms a 1 | (180 + 15) = 1/196 voltage divider.

Tank stimulus is 3.3Vpp - 2*0.7V (two emitter drops) = 1.9Vpp (square wave). If phase is dead nuts then Q is ~voltage gain.

*"3) Assuming that it would be nice to only have to compile one FPGA load ( to avoid the issue that my Pro causes), what would you consider to be an acceptable range of resonant frequencies for the DPLL without have to go in and change loop parameters?"*

Main DPLL parameters are set via powers of 2 (simple bit shifting gives "free" multiplication / division in HW) at FPGA build time. Some are independently adjustable, others are calculated off of these.

- The NCO (and thus LC) upper frequency limit is set by 1.536458MHz * 2^n, where n is a positive or negative integer (or zero). For example: for P3 the value of n for both the pitch and volume axes is 0 (1.5MHz) to accommodate their LC resonance points. You obviously don't want the LC resonance located too near to the NCO max, but not too far away either (for max numeric resolution).

- Inductor Q is a direct DPLL loop gain figure. Reducing Q by some factor will lower the loop gain by the same factor, which will lower the bandwidth of the DPLL. For example, for P3 a pitch axis Q of 200 gives -3dB @ 140Hz, a Q of 100 gives -3dB @ 70Hz. The loop gain can be independently adjusted (again via powers of 2) to compensate for whatever the actual Q is, in order to give the desired bandwidth.

- Inductor LC resonance frequency is an inverse (and more complex) loop gain figure, which will alter DPLL bandwidth. For example: for P3 lowering the pitch LC resonance frequency from 1.3MHz to 1MHz causes the bandwidth to go from 140Hz to 182.5Hz. Again, the loop gain can be independently adjusted to compensate for whatever the actual LC resonance frequency is, in order to give the desired bandwidth.

In conclusion: If an FPGA build is warranted it should be done. What makes it warranted can be something of a judgement call, but I can give you real bandwidth figures if you give me real LC frequency and Q numbers, and we can go from there. Or I can show you how to get these numbers from Quartus (it's pretty simple).

**[EDIT]** I changed the Vpp measurement to the AFE C divider output, which I trust more because it is lower impedance. This effectively doubled the calculated voltages and Qs!

**[EDIT2]** Using the AFE C divider for voltage measurements is ill-advised as it is likely too near the antenna and thus bathed in its strong electrostatic field. Measurement through a more distant C divider gives Q values in the neighborhood of 100, and concomitant voltage increases. Please read this post.